In the development of synchronous circuits, what are referred to as combinatorial blocks KBL(see FIGS. 1 and 2) are always located between registers (referenced input register RG1 and output register RG2 below). There are currently 3 principles of arranging combinatorial blocks and registers in order to adhere to the physically conditioned setup and hold times:
The transit time/delay time KBL-VZ of value changes through the combinatorial blocks KBL is shorter than the clock pulse period minus the setup time Setup/Hold-VZ and minus the signal propagation time RG-VZ through a register RG. This is shown in FIG. 1. A combinatorial block KBL is switched between an input register RG1 and an output register RG2. The registers RG1 and RG2 are driven by a clock pulse T.
The transit time of value changes through the combinatorial blocks KBL is greater by a factor N than a clock period of the clock pulse signal T. The outcome, however, is only picked up after N clock impulse signals at the exit of the output register RG2 behind the combinatorial blocks KBL.
The transit time of value changes through the combinatorial blocks KBL is greater by a factor N than a clock period of the clock pulse signal T. The outcome, however, is only stored in the output register RG2 behind the combinatorial blocks KBL after N clock pulse signals. To that end, an enable terminal EN at an output register RG2 is driven with a pulse that is delayed by N clock pulse signals and generated by a control circuit CON (see FIG. 2).
The transit time KBL-VZ through the combinatorial circuit KBL, however, is extremely value-dependent. This means that, in some cases, the output value could be clocked into the output register RG2 in the circuit arrangement (shown in FIG. 2) after M less than N cycles. The processing speed of a sequential logic system, in which the circuit arrangement (shown in FIG. 2) is embedded, could thus be increased.
German Letters Patent DE 36 06 406C2 discloses a circuit arrangement wherein combinatorial blocks are provided whose output signals are output to output registers which are switched behind these blocks. Further, sequential logic systems with combinatorial blocks and memory units are disclosed in German Patent DE 42 06 082C1 and European application EP 04 56 399A2.
It is an object of the present invention to modify the above circuit arrangement such that the temporal behavior is ameliorated.
In general terms the present invention is a circuit arrangement with combinatorial blocks arranged between registers. The output of the input register that is switched in front of the combinatorial blocks is connected with an analysis unit that analyzes the value of the output of the input register. The analysis unit sends an enable signal to the output register behind the combinatorial blocks when the output value of the combinatorial blocks has to be present according to the value of the output of the input register.
Advantageous developments of the present invention are as follows.
A spike filter is switched between the combinatorial blocks and the output register.
The combinatorial block is a multiplier. The analysis unit outputs an enable signal when the more significant places of the multiplicands are zero. A logical circuit is arranged behind the multiplier that sets the more significant places of the output value of the multiplier to zero in this case.